1. Field of the Invention
The present invention relates to a display control circuit for controlling the display operation of a display unit, such as a liquid crystal display.
2. Description of the Prior Art
Liquid crystal display units are widely used as display units in, for example, Japanese word processors and computers. In such liquid crystal display units, the entire screen comprises a multiplicity of display pixels arranged in a matrix fashion, with separate addresses set for individual display pixels so that display can be performed by adjusting the display condition of display pixels for individual addresses.
FIG. 1 is a diagram showing a display space 101 in a prior art liquid crystal display unit or the like. The display space 101 has an effective addressing range of from minimum address (-1024, -512) at upper left corner to maximum address (1023, 511) at lower right corner, bit requirements for which there are 11 bits (2.sup.10 =1024, where the most significant bit is a sign bit) in X direction, and 10 bits (2.sup.9 =512, where the most significant bit is a sign bit) in Y direction.
A display control circuit 104 is connected to the liquid crystal display unit 101 in FIG. 1 through for example, an 8-bit address bus 102 and a data bus 103. Therefore, when the display control circuit 104 is to carry out display control of the liquid crystal display unit in order to cause the display pixel at a single address to perform a display operation, it is necessary that access in X direction be had two times as shown in FIG. 2 (1), say, to low-order address data AL and high-order address data AH, each consisting of 8-bit address data D17 to D10. similarly, access in Y direction must be had two times as shown in FIG. 2 (2).
It is noted that most significant bit D17 in high-order address data AH is a sign bit. Therefore, in X direction, bits D17, D11, and D10 of the high-order address data AH, and the low-order address data AL are effective data. In Y direction, as FIG. 2 (2) shows, bits D17 and D10 of the high-order address data AH, and the low-order address data AL are effective data.
When any error should occur with respect to address data input from the display control unit 104 to the liquid crystal display unit 101, some undesired display may result within the effective address range of the liquid crystal display unit 101. When address data other than the effective address (1024, 512) shown in FIG. 1 are input to the liquid crystal display unit 101.
1024="0000010000000000"
which corresponds to the data configuration shown in FIG. 2 (1). In this case, bit D12 of the high-order address data AH is outside the effective address range in the liquid crystal display unit. Therefore, the address (0, 0) in FIG. 1 is designated by the effective address. In other words, an undesired display occurs with respect to the pixel at the address. Examples of address data resulting in such undesired occurrence are shown in Table 1 below.
TABLE 1 ______________________________________ Designated address Actual address ______________________________________ 400.sup.H (1024) 0.sup.H 800.sup.H (2048) 0.sup.H 1000.sup.H (4096) 0.sup.H 2000.sup.H (8192) 0.sup.H 4000.sup.H (16384) 0.sup.H 8000.sup.H (32768) 0.sup.H ______________________________________
In order to prevent occurrence of such undesired display, it has been usual practice to carry out software processing such that, where address data consist of, for example, bits smaller than a multiple of bits on the address bus 102, address data not within the scope of effective address are discriminated, when such data are input, so that no undesired display can occur within the effective display space. However, attempting to carry out such software processing each time when the display control circuit 104 accesses each individual address in the liquid crystal display unit 101 is very inconvenient in that such attempt results in decreased display efficiency. Further, inclusion of such processing functions involves a greater software burden.
For example, the case of a liquid crystal display unit of the simple matrix type is discussed. Such as display unit includes pluralities of belt-like transparent electrodes formed as row and column electrodes in intersecting relation on a pair of transparent bases, whereby matrix-form addresses are set in the entire display space of the liquid crystal display unit. A row drive circuit and a column drive circuit are connected to the liquid crystal display unit, and CPU (central processing circuit), for example, is connected to both the row drive circuit and the column drive circuit. The row drive circuit scans row electrodes in the liquid crystal display unit in the row of line-writing direction to longitudinally set address data, whereas the column drive circuit scans column electrodes in the column or column-writing direction to transversely set address data.
For the purpose of display by the liquid crystal display unit through such a display control circuit, segments are set for individual unit display spaces of 8 bits each, for example, in the line-writing direction in the display space, and access is had for each of the segments. Therefore, when display data of 8-bit each which extend over a plurality of unit display spaces are to be displayed, CPU processes address data by software and outputs processed address data to the row drive circuit. When display data are to be written in the display space for display by unit display spaces of 8-bit each, it is very difficult to process address data by software in both row and column directions, because such processing requires software containing extremely large amounts of programs.
In the foregoing prior art arrangement, processing of address data in CPU is carried out by software processing, and this involves a problem that CPU is excessively loaded. Another problem is that it is impracticable to achieve bidirectional display operation, or display operation in both the row direction and the column direction, which means that the utility of the prior art arrangement is rather limited.
FIG. 3 is a block diagram showing the arrangement of a typical prior-art display control circuit 104. The display control circuit 104 comprises a common drive circuit 105 for driving a common electrode of, for example, a liquid crystal display element 101 of the simple matrix type, segment drive circuits 106 for driving segment electrodes, and CPU (central processing unit) 107 for outputting address data and display data to the drive circuits 105, 106. The component circuits are interconnected by a bus line 108.
CPU107 comprises a write buffer 109 for retaining write data being written in predetermined addresses in the liquid crystal element 101, a read buffer 110 for storage of display data stored in the segment drive circuits 106, displayed by the liquid crystal display element 101 and read by CPU107, an arithmetic circuit 111 for carrying out one of plural kinds arithmetic operations with respect to data stored in the buffers 109, 110, and a result buffer 112 for retaining arithmetic operation results and transferring data to the segment drive circuits 106 at predetermined time intervals. Each of the buffers 109, 110, 112 has a capacity of, for example, 8 bits. It is noted that symbol "." in FIG. 3 represents most significant bit (MSB) of the 8-bit data.
Next, the manner in which a write loop is executed for successively writing display data within a range of successive addresses in the liquid crystal display element 101 will be discussed.
Write address in which first display data is written is transferred from CPU107 to the segment drive circuit 106, and then display data are set in the write buffer 109 within CPU107. Then, predetermined arithmetic operation is carried out in the arithmetic circuit 111. The result is stored in the result buffer 112 and is then transferred to the segment drive circuit 106. Subsequently, similar processing is carried out with respect to each next successive write address.
That is, in the prior arrangement, when write instructions are to be successively executed over a range of successive addresses in the liquid crystal display element 101, it is necessary that write address be designated for each address. Also, it is necessary to follow a procedure such that the operation result in the result buffer 112 be temporarily saved in another place and, at a next write instruction, be read again for transfer to segment drive circuit 106. Such processing, when it is to be done by CPU107, is carried out through software processing, which is rather disadvantageous from the standpoint of time economy.
For execution of a loop for block transfer for reading display data from the segment drive circuit 106, read address for display data to be read is initially transferred from CPU107 to the segment drive circuit 106 and, in turn, read data for the address is transferred to CPU107 and is stored in the read buffer 110. A series of arithmetic operation is carried out with respect to the read data at the arithmetic circuit 111, and the operation results are stored in the result buffer 112. Write address is transferred to the segment drive circuit 106 according to same procedure as above state, and display data is likewise transferred. Such block transfer makes it necessary to repeat the foregoing operation by software processing for each 8 bits. In this case, too, such a problem as stated above is involved.
A stated earlier, where display operation is carried out by software processing, there is involved considerable software burden, and the procedure for such processing is time-consuming, which makes it difficult to achieve high-speed display.
In liquid crystal display units of the type having a common electrode and segment electrodes formed respectively on a pair of transparent bases, with a liquid crystal layer interposed between the electrodes, addresses are set in a display space in a matrix fashion, for each of which addresses is carried out display control. To such a display unit having such display space set therein are connected a column address output circuit for outputting column address data, and a row address output circuit for outputting row address data. Where the display space in such a liquid crystal display unit is large-sized in the row direction, a plurality of row address output circuits are employed, and display control is carried out for each predetermined range of addresses. The row address output circuits and the column address output circuit are connected to a CPU (central processing circuit) including a microprocessor, etc. which supplies address data and display data to the address output circuits.
In such large-type liquid crystal display unit, CPU selects one of the plurality of row address output circuits according to each virtual display address in the display space, and the selected row address output circuit outputs actual address data within its scope of control. This process of operation is carried out by software through CPU. In the prior art, it has been necessary to carry out such software processing for each address in the display space. As such, the prior art practice of display processing has been time-consuming and, especially in the case of a portable data processing unit of the battery drive system, it has been difficult to supply such a comparatively large amount of power as is required for high-speed operation of CPU, which fact has made the foregoing problems all the more conspicuous.